1. Field of the Invention
The present invention generally relates to multi-write port registers and, more particularly, to a multi-write port register with a local clock buffer (LCB) having a logic function controlling the register's write-enable input port and handling all the critical timing functions of the register.
2. Background Description
The design of multi-write port registers becomes increasingly complex and difficult as the number of simultaneous write ports required for the design increases. The design is further complicated by requirements for maskable fields or the need for set/reset/sticky-write ports implemented in the registers. A "sticky-write" of a register is a write operation that is dependent on the contents of the data being written to the register. For example, in a sticky-1 write operation, only a "1" can be written. A "0" attempted write will be repressed.
In a typical register design, Write-port Data is sent to the Write-port Bit Lines (BLs) during the CLKC cycle of the clock signal, and the register cells to be written will have a Write Enable (WE) signal applied to the cells during the following CLKT cycle. The register will be continually written with data coming from its Write-port BLs as long as the WE signal is asserted. Consequently, the WE signal must be deasserted at or before the next CLKC signal is asserted because the next set of Write-port Data is being sent to the BLs during this cycle. If the WE signal is not deasserted in time, there is a risk of unintentionally writing the new write data into the registers.